Field of the Invention
The invention relates to a circuit configuration for deactivating word lines in a memory matrix. Each of the word lines is connected to a controllable connection device for connecting the relevant word line to a common supply line system carrying a deactivation potential for the word line. A control circuit which in response to the deactivation command, produces a deactivation control signal that turns on the controllable connection device.
In normal digital information memories, the memory cells form a matrix of rows and columns. To select a memory cell for the purposes of writing or reading, a word line associated with the relevant row is activated and a bit line associated with the relevant column is driven. The selected activation of the word lines, that is to say the xe2x80x9caddressingxe2x80x9d of the rows in the matrix, is normally performed by a row address decoder which has outputs individually connected to the word lines and inputs for receiving the bits of a digital row address.
Similarly, the selective driving of the bit lines is performed by a column address decoder.
A word line is activated by applying an activation potential which conditions the switching transistors of the associated memory cells such that the charges stored in the memory cells are transferred to the respective bit lines. The activation potential is applied by the row address decoder that selects the respective word line to be activated.
Once the read or write operation has been performed, the word line is deactivated again by bringing it to a deactivation potential which turns off the cell transistors. The deactivation potential is applied by the row address decoder by turning on a connection device that is individually associated with the relevant word line and connects the relevant word line to a supply line system carrying the potential relating thereto. The connection device is normally a transistor switch that is turned on fully in response to a deactivation command.
In some tests carried out on memory matrices for the purposes of a checking operation, word lines are temporarily activated and subsequently deactivated without performing a write or read operation during activation. The test activation can be used, for example, to detect a risk of leakage currents, in particular when, in this context, the activation is maintained over a relatively long period and/or is carried out using a slightly increased activation potential. Such leakage currents can flow, by way of example, from the activated word lines to memory cells on adjacent unactivated word lines. Any leakage currents arising therefore influence the charge state of memory cells on unactivated word lines, which can be established by subsequently checked the memory contents thereof. To save test time, the test activation is preferably carried out on a plurality of word lines at the same time, specifically using such a selection that the activated word lines have unactivated exemplars adjacent to them. This xe2x80x9cmultiple word line selectxe2x80x9d, which can be preprogrammed in the row address decoder, should, by way of example, contain the selection of each fourth word line for activation, while the word lines situated in between are kept inactive.
When a plurality of active word lines are deactivated at the same time, the discharge currents flowing via the associated deactivation transistors add up to form a relatively high total current which burdens the network carrying the deactivation potential. In this context, the network primarily contains the inactive word lines and wiring in the row address decoder, which wiring is relatively narrow for space reasons, and thus has a relatively high resistance, and also distributes the deactivation potential to associated connections of other elements of the decoder. As a result of the high resistance of the metallized area forming the wiring, the simultaneous deactivation of the active word lines produces a resistive voltage drop across the network, which voltage drop burdens the other, inactive word lines, most severely the directly adjacent exemplars. In this case, a relatively large voltage elevation occurs which is proportional to the number of active word lines and is thus proportional to the time saving aimed for. The voltage elevation that occurs causes a reduction in the blocking effect of the associated cell transistors in the affected word lines, and this can erase some or all of the information in connected cells.
To prevent this risk, the number of word lines which are respectively selected at the same time for the multiple word line select has been kept down to date. In consequence, however, a longer test time was needed. One alternative would be to configure the deactivation potential network to have a very low resistance, but this would require wider metallized areas and is undesirable for space reasons.
It is accordingly an object of the invention to provide a circuit configuration for deactivating word lines in a memory matrix that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which permit even a relatively large number of active word lines on a memory matrix to be deactivated at the same time and without perturbing accompanying effects.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for deactivating word lines in a memory matrix of a memory. The circuit configuration contains a common supply line system carrying a deactivation potential for the word lines, and controllable connection devices connected to the common supply line and to be connected to the word lines. The controllable connecting devices connect each of the word lines to the common supply line system carrying the deactivation potential for the word lines. A control circuit is provided and has an output connected to the controllable connection devices. The control circuit receives a deactivation command and in response to the deactivation command produces a deactivation control signal available at the output. The deactivation control signal turns on the controllable connection devices resulting in turned-on controllable connection devices. The control circuit has a reduction device connected to the output and the reduction device can be switched on selectively and which, when switched on, limits currents flowing through the turned-on controllable connection devices to such an extent that a total current flowing through the common supply line system does not exceed a prescribed value.
Accordingly, the invention is implemented on a circuit configuration for deactivating the word lines in the memory matrix. Each of which has the controllable connection device for connecting the relevant word line to the common supply line system carrying the deactivation potential for the word lines. The control circuit is provided which, in response to a deactivation command, produces a deactivation control signal that turns on the controllable connection devices. According to the invention, the control circuit contains a reduction device which can be switched on selectively and which, when switched on, limits the currents flowing through the turned-on connection devices to such an extent that the total current flowing via the supply line system does not exceed a prescribed value.
The inventively provided reduction device permits large currents in the supply line system carrying the deactivation potential, and hence the aforementioned voltage elevations normally to be dreaded when the word lines are deactivated at the same time, to be reduced or prevented entirely. It is thus possible to carry out tests in the multiple word line select using far more word lines than previously, and thus to shorten the total test time on the memory matrix.
The desired current limiting can be achieved by changing the ratio of the effective resistances of the word line connection device and the deactivation potential supply line system. By increasing the size of the resistance of the connection devices between the word line and the deactivation potential supply line system, the discharge current of the active word lines is better distributed over all the inactive word lines. Accordingly, one advantageous embodiment of the inventive reduction device contains means for increasing the electrical resistance of the connection devices.
This means may provide each connection device with a series resistor that is normally bridged and is activated only when a plurality of active word lines is intended to be deactivated at the same time. However, this requires a multiplicity of additional components and interconnections. A more elegant path can be taken if each connection device contains, as is known per se, a deactivation transistor whose primary current path is situated between the relevant word line and the supply line system and whose control electrode receives the deactivation control signal. In this case, the increase in the size of the electrical resistance of the connection device can be achieved by reducing the voltage swing for the deactivation control signal, that is to say by reducing the amplitude of the signal, which turns on the transistor. In addition or as an alternative, the inventive reduction device may contain means for extending the rise time of the deactivation control signal. This likewise achieves current limiting, because high discharge current peaks are prevented, such as otherwise arise when the deactivation control signal has a high edge gradient.
In accordance with an added feature of the invention, each of the controllable connection devices have a deactivation transistor with a primary current path connected between one of the word lines and the common supply line system. The deactivation transistor has a control electrode connected to the output of the control circuit and the control electrode receives the deactivation control signal. The reduction device has means for reducing an amplitude of the deactivation control signal.
In accordance with an additional feature of the invention, the reduction device has means for reducing a gradient of a leading edge of the deactivation control signal.
In accordance with another feature of the invention, a first terminal for receiving a first potential, a second terminal for receiving a second potential, and a third terminal for receiving a third potential are provided. A first current path is connected between the first terminal and the output.
The first current path, only when it is on, connects the control electrode of the deactivation transistor to the first potential which turns off the deactivation transistor. A second current path is connected between the output and the second terminal. The second current path, only when it is on, connects the control electrode of the deactivation transistor to the second potential which drives the deactivation transistor to saturation. A third current path is connected between the output and the third terminal. The third current path, only when it is on, connects the control electrode of the deactivation transistor to the third potential for biasing the deactivation transistor in a forward direction. The third current path contains the means for reducing the amplitude and the means for reducing the gradient of the leading edge of the deactivation control signal.
In accordance with a further feature of the invention, the means for reducing the amplitude of the deactivation control signal adjusts the third potential by a given value resulting in the deactivation control signal that biases the deactivation transistor in a state having limited conductivity.
In accordance with a further added feature of the invention, the third current path contains a diode or a transistor wired up as a diode having a threshold voltage that is subtracted, when the third current path is on, from the third potential.
In accordance with a further additional feature of the invention, the means for reducing the gradient of the leading edge of the deactivation control signal includes at least one element having a perceptible non-reactive resistance that forms part of the third current path.
In accordance with another further feature of the invention, the element with the non-reactive resistance is a primary current path of a transistor which is turned on in order to switch on the third current path.
In accordance with a concomitant feature of the invention, the control circuit has a first input for applying a mode setting signal, a second input for applying a binary command signal, and a logic combination device connected to the first input, the second input, the first current path, the second current path and the third current path. The logic combination device keeps only the first current path switched on whenever and only when the binary command signal has a first binary value. The logic combination device keeps the second current path switched on whenever and only when the binary command signal has a second binary value and the mode setting signal has a particular binary value. The logic combination device switches on only the third current path whenever and only when the binary command signal has the second binary value and the mode setting signal has the binary value other than the particular binary value.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for deactivating word lines in a memory matrix, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.